// +build l476xx

// Peripheral: DAC_Periph  Digital to Analog Converter.
// Instances:
//  DAC   mmap.DAC1_BASE
//  DAC1  mmap.DAC1_BASE
// Registers:
//  0x00 32  CR      Control register.
//  0x04 32  SWTRIGR Software trigger register.
//  0x08 32  DHR12R1 Channel1 12-bit right-aligned data holding register.
//  0x0C 32  DHR12L1 Channel1 12-bit left aligned data holding register.
//  0x10 32  DHR8R1  Channel1 8-bit right aligned data holding register.
//  0x14 32  DHR12R2 Channel2 12-bit right aligned data holding register.
//  0x18 32  DHR12L2 Channel2 12-bit left aligned data holding register.
//  0x1C 32  DHR8R2  Channel2 8-bit right-aligned data holding register.
//  0x20 32  DHR12RD Dual DAC 12-bit right-aligned data holding register.
//  0x24 32  DHR12LD DUAL DAC 12-bit left aligned data holding register.
//  0x28 32  DHR8RD  DUAL DAC 8-bit right aligned data holding register.
//  0x2C 32  DOR1    Channel1 data output register.
//  0x30 32  DOR2    Channel2 data output register.
//  0x34 32  SR      Status register.
//  0x38 32  CCR     Calibration control register.
//  0x3C 32  MCR     Mode control register.
//  0x40 32  SHSR1   Sample and Hold sample time register 1.
//  0x44 32  SHSR2   Sample and Hold sample time register 2.
//  0x48 32  SHHR    Sample and Hold hold time register.
//  0x4C 32  SHRR    Sample and Hold refresh time register.
// Import:
//  stm32/o/l476xx/mmap
package dac

// DO NOT EDIT THIS FILE. GENERATED BY stm32xgen.

const (
	EN1       CR = 0x01 << 0  //+ DAC channel1 enable.
	TEN1      CR = 0x01 << 2  //+ DAC channel1 Trigger enable.
	TSEL1     CR = 0x07 << 3  //+ TSEL1[2:0] (DAC channel1 Trigger selection).
	WAVE1     CR = 0x03 << 6  //+ WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable).
	MAMP1     CR = 0x0F << 8  //+ MAMP1[3:0] (DAC channel1 Mask/Amplitude selector).
	DMAEN1    CR = 0x01 << 12 //+ DAC channel1 DMA enable.
	DMAUDRIE1 CR = 0x01 << 13 //+ DAC channel 1 DMA underrun interrupt enable  >.
	CEN1      CR = 0x01 << 14 //+ DAC channel 1 calibration enable >.
	EN2       CR = 0x01 << 16 //+ DAC channel2 enable.
	TEN2      CR = 0x01 << 18 //+ DAC channel2 Trigger enable.
	TSEL2     CR = 0x07 << 19 //+ TSEL2[2:0] (DAC channel2 Trigger selection).
	WAVE2     CR = 0x03 << 22 //+ WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable).
	MAMP2     CR = 0x0F << 24 //+ MAMP2[3:0] (DAC channel2 Mask/Amplitude selector).
	DMAEN2    CR = 0x01 << 28 //+ DAC channel2 DMA enabled.
	DMAUDRIE2 CR = 0x01 << 29 //+ DAC channel2 DMA underrun interrupt enable  >.
	CEN2      CR = 0x01 << 30 //+ DAC channel2 calibration enable >.
)

const (
	EN1n       = 0
	TEN1n      = 2
	TSEL1n     = 3
	WAVE1n     = 6
	MAMP1n     = 8
	DMAEN1n    = 12
	DMAUDRIE1n = 13
	CEN1n      = 14
	EN2n       = 16
	TEN2n      = 18
	TSEL2n     = 19
	WAVE2n     = 22
	MAMP2n     = 24
	DMAEN2n    = 28
	DMAUDRIE2n = 29
	CEN2n      = 30
)

const (
	SWTRIG1 SWTRIGR = 0x01 << 0 //+ DAC channel1 software trigger.
	SWTRIG2 SWTRIGR = 0x01 << 1 //+ DAC channel2 software trigger.
)

const (
	SWTRIG1n = 0
	SWTRIG2n = 1
)

const (
	DACC1DHR DHR12R1 = 0xFFF << 0 //+ DAC channel1 12-bit Right aligned data.
)

const (
	DACC1DHRn = 0
)

const (
	DACC1DHR DHR12L1 = 0xFFF << 4 //+ DAC channel1 12-bit Left aligned data.
)

const (
	DACC1DHRn = 4
)

const (
	DACC1DHR DHR8R1 = 0xFF << 0 //+ DAC channel1 8-bit Right aligned data.
)

const (
	DACC1DHRn = 0
)

const (
	DACC2DHR DHR12R2 = 0xFFF << 0 //+ DAC channel2 12-bit Right aligned data.
)

const (
	DACC2DHRn = 0
)

const (
	DACC2DHR DHR12L2 = 0xFFF << 4 //+ DAC channel2 12-bit Left aligned data.
)

const (
	DACC2DHRn = 4
)

const (
	DACC2DHR DHR8R2 = 0xFF << 0 //+ DAC channel2 8-bit Right aligned data.
)

const (
	DACC2DHRn = 0
)

const (
	DACC1DHR DHR12RD = 0xFFF << 0  //+ DAC channel1 12-bit Right aligned data.
	DACC2DHR DHR12RD = 0xFFF << 16 //+ DAC channel2 12-bit Right aligned data.
)

const (
	DACC1DHRn = 0
	DACC2DHRn = 16
)

const (
	DACC1DHR DHR12LD = 0xFFF << 4  //+ DAC channel1 12-bit Left aligned data.
	DACC2DHR DHR12LD = 0xFFF << 20 //+ DAC channel2 12-bit Left aligned data.
)

const (
	DACC1DHRn = 4
	DACC2DHRn = 20
)

const (
	DACC1DHR DHR8RD = 0xFF << 0 //+ DAC channel1 8-bit Right aligned data.
	DACC2DHR DHR8RD = 0xFF << 8 //+ DAC channel2 8-bit Right aligned data.
)

const (
	DACC1DHRn = 0
	DACC2DHRn = 8
)

const (
	DACC1DOR DOR1 = 0xFFF << 0 //+ DAC channel1 data output.
)

const (
	DACC1DORn = 0
)

const (
	DACC2DOR DOR2 = 0xFFF << 0 //+ DAC channel2 data output.
)

const (
	DACC2DORn = 0
)

const (
	DMAUDR1   SR = 0x01 << 13 //+ DAC channel1 DMA underrun flag.
	CAL_FLAG1 SR = 0x01 << 14 //+ DAC channel1 calibration offset status.
	BWST1     SR = 0x01 << 15 //+ DAC channel1 busy writing sample time flag.
	DMAUDR2   SR = 0x01 << 29 //+ DAC channel2 DMA underrun flag.
	CAL_FLAG2 SR = 0x01 << 30 //+ DAC channel2 calibration offset status.
	BWST2     SR = 0x01 << 31 //+ DAC channel2 busy writing sample time flag.
)

const (
	DMAUDR1n   = 13
	CAL_FLAG1n = 14
	BWST1n     = 15
	DMAUDR2n   = 29
	CAL_FLAG2n = 30
	BWST2n     = 31
)

const (
	OTRIM1 CCR = 0x1F << 0  //+ DAC channel1 offset trimming value.
	OTRIM2 CCR = 0x1F << 16 //+ DAC channel2 offset trimming value.
)

const (
	OTRIM1n = 0
	OTRIM2n = 16
)

const (
	MODE1 MCR = 0x07 << 0  //+ MODE1[2:0] (DAC channel1 mode).
	MODE2 MCR = 0x07 << 16 //+ MODE2[2:0] (DAC channel2 mode).
)

const (
	MODE1n = 0
	MODE2n = 16
)

const (
	TSAMPLE1 SHSR1 = 0x3FF << 0 //+ DAC channel1 sample time.
)

const (
	TSAMPLE1n = 0
)

const (
	TSAMPLE2 SHSR2 = 0x3FF << 0 //+ DAC channel2 sample time.
)

const (
	TSAMPLE2n = 0
)

const (
	THOLD1 SHHR = 0x3FF << 0  //+ DAC channel1 hold time.
	THOLD2 SHHR = 0x3FF << 16 //+ DAC channel2 hold time.
)

const (
	THOLD1n = 0
	THOLD2n = 16
)

const (
	TREFRESH1 SHRR = 0xFF << 0  //+ DAC channel1 refresh time.
	TREFRESH2 SHRR = 0xFF << 16 //+ DAC channel2 refresh time.
)

const (
	TREFRESH1n = 0
	TREFRESH2n = 16
)
